The Processor
Datapath, Control & Pipelining
Master processor architecture from the ground up — datapath components, control unit design, 5-stage pipelining, hazard detection & resolution, forwarding, and performance optimization.
📚 Lecture Roadmap
Combinational & sequential elements, ALU, MUX, registers, building blocks of processor
R-format, load/store, branch instructions, full single-cycle datapath
Control signals, ALU control, main control, opcode decoding
5-stage pipeline (IF, ID, EX, MEM, WB), pipeline registers, performance
Structural, data, control hazards; forwarding, stalling, branch prediction
Review formulas, quizzes, performance calculations
📖 Study Guide
🎯 Key Learning Outcomes
- Understand how processor executes instructions
- Design and analyze datapath components
- Generate control signals from opcodes
- Explain 5-stage pipelining and its benefits
- Identify and resolve pipeline hazards
- Implement forwarding to eliminate stalls
- Calculate pipeline performance (speedup, CPI)
🔑 Essential Formulas
- CPU Time: IC × CPI × Clock Period
- Pipeline Cycles: (n + k - 1) where n=instructions, k=stages
- Speedup: Non-pipelined Time / Pipelined Time
- CPI with Hazards: 1 + Stalls per Instruction
- Branch Penalty: Branch% × Misprediction% × Cycles
💡 Study Tips
- Draw diagrams: Sketch datapath and trace instruction execution
- Practice hazard detection: Look for dependencies in code sequences
- Use pipeline tables: Track instructions through stages
- Memorize control signals: Know values for R-type, lw, sw, beq
- Calculate CPI: Include all stall cycles from hazards
⚠️ Common Mistakes
- ❌ Confusing latency and throughput: Pipelining increases throughput, NOT latency
- ❌ Forgetting load-use stalls: Forwarding can't eliminate all hazards
- ❌ Wrong forwarding priority: EX hazard > MEM hazard
- ❌ Ignoring branch delay: MIPS has 1 delay slot instruction
- ❌ CPI calculation errors: Don't forget pipeline fill cycles (k-1)