📝 Assignment 3 — CSE 532 Project
Full CPU
Verilog Implementation
Design the complete 32-bit single-cycle CPU in Verilog — ALU, Register File, Control Unit, Data Memory. Add JAL, JR, SRL, SLL. Test with your OS program. বাংলা ব্যাখ্যা সহ।
16 Sections
বাংলা + English
JAL/JR/SLL/SRL
Complete Verilog Code
📌 Prerequisites
Lecture 4: Verilog & Lecture 3: Datapath required. Assignment 1 (ISA) & Assignment 2 (OS program) should be complete.